3 January 2000
Source: Fax of 26 pages from Anonymous.

MODULAR EXPONENTIATION PROCESSOR

(NLC0048 LSI)

SHORT FORM DATA SHEET

VERSION 1.0

August 1, 1996

NTT Electronics Technology Corporation

This document contains information on a product under development. NTT Electronics Technology reserves the right to change or discontinue the product without notice.

1.  GENERAL INFORMATION

2.  FUNCTIONAL DESCRIPTION

     2.1 Processor operation

     2.2 Block diagram

3.  SIGNAL DESCRIPTION

4.  REGISTERS

     4.1 Register Table

     4.2 Register Description

          4.2.1 Status0 Register
          4.2.2 Status1 Register
          4.2.3 Command Register
          4.3.4 Data Register

5.  STATUS DESCRIPTION

6.  TYPICAL USAGE

     6.1 Operation example using Exp0, Mod0, Bas0

     6.2 Operation example using Exp1, Mod1, Bas1

7.  ELECTRICAL CHARACTERISTICS

     7.1 Maximum ratings

     7.2 Guaranteed Operating Ratings

     7.3 DC Characteristics

     7.4 AC Characteristics

8.  MECHANICAL DATA

     8.1 PIN Assignments

     8.2 Package Dimensions

---

1.  GENERAL INFORMATION

This short form data sheet provides general information on the design and functionality of the single chip Modular Exponentiation Processor (NLC0048). This LSI can perform the high-speed modular exponentiation processing required in RSA public key cryptography and Diffie-Hellman key distribution systems.

• Major features of NLC0048 are as follows:
  
• high-speed M^e mod n operation within 0.1 second when all parameters have 1024 bit length.
  
• arbitrary parameter length up to 1024 bits on condition that |M| < |n|

                        |M|, |n|: the bit length of M, n respectively

• two register groups (exp0, mod0 and exp1, mod1) permit two-way communication.
  
• the byte length of the data to be read out is attached to the first byte of the result data.

• battery backup capability and the read protection function of the Exp0 register makes it possible to hold an RSA private key.
  

2.  FUNCTIONAL DESCRIPTION

2.1 PROCESSOR OPERATION

The arithmetical operations of the RSA algorithm are multiplication and division involving integers that are hundreds of digits long. The redundancy binary representation method reduces carry propagation delay and makes the operation exceedingly fast. In the conventional method, however, the most significant bit of the divisor must always be '1' to solve the quotient. This means only certain bit-length keys are available. In order to solve this problem, if the bit length of the divisor is less than 1024, it is automatically multiplied so that it becomes 1024, and the message to be operated is also multiplied by the same multiple. Then the operational result to be read out is divided by the same multiple at the output stage. The operational flow is as follows:

(1) The exponent parameter is written in the Exp0 or Exp1 register from the most significant byte. The first byte of all 'o' is discarded automatically. If the exponent is already written, this operation is unnecessary.

(2) The modulus parameter is written in the Mod0 or Mod1 register from the most significant byte. The input controller multiplies 2^k so that the bit length of the modulus parameter becomes 1024. The input data is multiplied by 2^k in the LSI.

(3) The start command triggers the operation. The calculation is perfomred in the iterative bit slice macro. The round number depends on the bit length of the exponent in Exp0 or Exp1.

(4) The result data is divided by 2^k, and a byte is attached to the first byte to be read out which indicates the effective byte length of the result data. The data sent out from the most significant byte.

2.2 BLOCK DIAGRAM

(1) Input Buffer / Bit Buffer

Input data is sequentially induced to the input buffer by 8 bits. When writing in the Mod0/1 register, the position of the most significant '1' in the input stream is searched for, and a new 8 bit byte is configured so that the most significant bit of the byte becomes '1'. Then the new byte is transmitted to the Byte Shifter. The shift count in the Input Bit Shifter is memorized in the shift counter and the total effective byte length of the modulus data is calculated in this procedure. The input data to be operated, which will finally be written in the Bas0/1 register, is also shifted by the same count as the modulus data shifted in the Input Bit Shifter.

The exponent data to be written in Exp0/Exp1 is transmitted transparently to each register.

(2) Output Buffer / Bit Shifter

When reading from the Result and Mod0/1 register, the 'o' bits, whose number was saved in the shift counter in the Input Bit Shifter, are fulfilled at the upper part of the first byte to be read out. If all bits in the first byte to be read out become 'o', this byte is discarded and the next byte is checked. The total effective byte length, which is calculated from the effective byte length of the modulus data and the discarded bytes in the Output Bit Shifter, is attached to the first byte of the output data.

When reading from the Exp0/Exp1 register, the effective byte length is also attached to the first byte of the read out data, which is memorized in each register at the writing stage.

(3) Byte Shifter

The input data arranged at the Input Bit Shifter is induced to the Byte Shifter except in the case of Exp0/12 writing. When writing is completed, all bytes in the Byte Shifter are shifted so that the most significant byte is not vacant. When register reading except for Exp0/1, the output data is latched in this Byte Shifter, and transmitted to the Output Bit Shifter by 8 bits.

(4) Exp0/Exp1 Register

Exponent data are stored in each register with their effective byte length. The contents of Exp0 and its byte length can be held without a power supply by the backup battery.

(5) Bas0/Bas1 Register

The registers which hold the data to be operated.

(6) Mod0/Mod1 Register

The registers which hold the modulus data.

(7) Result Register

The register which holds the intermediate data during operation and finally holds the result.

(8) Redundant Binary Calculation Block

The modulus exponentiation operation is carried out in this block. The multiplication or division of 1024 bits data is completed within one system clock.

(9) Overflow Buffer

The Overflow Buffer receives data of more than 1024 bits which results from the multiplication of two numbers both with a 1024 bit length. The contents are used at the division stage.

(10) Redundant Binary Calculation Controller

The controller which generates signals and supplies timing signals to each block of the LSI.

(11) Sleep Controller

The sleep controller stops the inner clock to reduce power consumption.

3.  SIGNAL DESCRIPTION

Table 3.1 Signal List (1/2)

4.  REGISTERS

4.1 Register Table

Table 4.1 Register Summary

Status0/Status1: Read Only Register                 Command/Data: Read-Write Register

D1 bit in Status0 is always '1', and D4 bit in Command Register is unused.

Data register is not a real one but is a general name of the Result, Mod0/1, Exp0/1 and Bas0/1 registers.

4.2 Register Description

4.2.1 Status0 Register

LSI status is observed from this register when calculation is performed with Exp0, Mod0 and Bas0.

(1) Error

Next operation will cause Error to turn on.

(a) Read/write option in Data Register is performed when I/O ready bit is "low".

(b) Write operation is carried out when command bit is "low".

(2) I/O Ready

Before writing data in the Mod0, Exp0 and Bas0 registers, the register to be accessed and the write/read operation must be designated by writing both Register and W/R* field in the Command register. The registers are accessible when the I/O ready flag is "high". After completing the read operation from the Result, Mod0, Exp0 and Bas0 registers, the I/O ready flag switches off.

(3) Command ready

This flag indicates that the write operation in the Command register is available. The Status register must always be checked before the Command write operation. A read operation from the Command register is always possible even when the Command ready flag is "low". LSI operation is not guaranteed if command register writing is carried out when the command ready flag is off. One exception is that Abor command writing is available during an arithmetic operation.

(4) Busy

This flag indicates that an arithmetic operation is in progress. Abort command is available only when this flag is "high".

(5) Busy0

This flag indicates that an arithmetic operation is in progress using the Mod0, Exp0 and Bas0 registers.

(6) Mod0

This flag indicates that data is already written in Mod0.

(7) Exp0

This flag is always "high" because Exp0 can be held by the battery.

(8) Bas0

This flag indicates that data is already written in Bas0. If a writing operation in the Mod0 or Bas1 register is undertaken after writing in the Bas0 register, the Bas0 flag will switch off and subsequent successive operation is not guaranteed.

4.2.2 Status1 Register

LSI status is observed from this register when a calculation is performed with Exp1, Mod1 and Bas1.

(1) Error

This flag has the same meaning as Status0.

(2) I/O Ready

Before writing data in Mod1, Exp1 and Bas1 registers, the register accessed and the write/read operation must be designated by writing both Register and W/R* field in the Command register. The registers accessible when the I/O ready flag is "high". After a read operation from the Mod1, Exp1 and Bas1 registers, the I/O ready flag switches off.

(3) Command ready

This flag has the same meaning as in Status0.

(4) Busy

This flag has the same meaning as in Status0.

(5) Busy1

This flag indicates that an arithmetical operation is in progress using the Mod1, Exp1 and Bas1 registers.

(6) Mod1

This flag indicates that data is already written in Mod1.

(7) Exp1

This flag indicates that data is already written in Exp1.

(8) Bas1

This flag indicates that data is already written in Bas1. If a writing operation in the Mod1 or Bas0 register is completed after writing to Bas1 register, the Bas1 flag will switch off and subsequent successive operation is not guaranteed.

4.2.3 Command Register

(1) Reset

Writing the Command Register with "high" Reset field will initialize all the registers in the LSI except Exp0 and its byte length register. This command is always available except under Sleep mode. The reading result of the Reset filed is always "low".

(2) Abort

The Abort command stops the calculation of modular exponentiation, and makes the Result register unavailable. The simultaneous designation of both the Start and Abort commands invalidates the LSI operation. The reading result of the Abort field is always "low".

(3) Start

The Start command starts the calculation after byte shifting in the Byte Shifter. The simultaneous designation of both the Start and Abort commands invalidates the LSI operation. The reading result of the Start field is always "low".

(4) W/R*

This field designates write operation ("high") or read operation ("low") to the registers assigned by the Register field.

(5) Register

The Register field specifies the register to be accessed in the following read or write cycle.

(a) Result Register (Read only)

This register is assigned when the modular exponentiation is read out. The first byte is the byte length of the resulted data, and is followed by the result data stream.

Command write for reading from the Result Register is possible just after the Start command, but the actual reading operation can be performed after I/O ready switches on. The contents in the Result register are held till the next Start or Reset command.

(b) Mod1 Register (Read/Write)

This register is assigned when read or write access to Mod1 is performed. The first byte is the byte length of the contents, and is followed by data stream in Mod1.

Table 4.1 Register Table

D2	D1	D0	Register Name	R, W	at power off
1	1	1	Result	R	volatile
1	1	0	Mod1	R/W	volatile
1	0	1	Mod0	R/W	volatile
1	0	0	Exp1	R/W	volatile
0	1	1	Exp0	W	nonvolatile
0	1	0	Bas1	R/W	volatile
0	0	1	Bas0	R/W	volatile
0	0	0	No-op	-	-

(c) Mod0 Register (Read/Write)

This register is assigned when read or write access to Mod0 is performed. The first byte is the byte length of the contents, and is followed by the data stream in Mod0.

(d) Exp1 Register (Read/Write)

This register is assigned when read or write access to Exp1 is performed. The first byte is the byte length of the contents, and is followed by the data stream in Exp1.

(e) Exp0 Register (Write only)

This register is assigned when write access to Exp0 is performed. Even after power off, the contents in Exp0 and its byte length can be held by the backup battery. They are also held despite the Reset command. Without the backup battery, the contents after power on is undecided.

(f) Bas1 Register (Read/Write)

This register is assigned when read or write access to Bas1 is performed. The first byte is the byte length of the contents, and followed by the data stream in Bas1. Before writing in the Bas1 register, writing in Mod1 must be completed. Mod1 or Bas0 writing after Bas1 writing invalidates the LSI operation.

(g) Bas0 Register (Read/Write)

This register is assigned when read or write access to Bas0 is performed. The first byte is the byte length of the contents, and followed by the data stream in Bas0. Before writing in the Bas0 register, writing in Mod1 must be completed. Mod1 or Bas0 writing after Bas0 writing invalidates the LSI operation.

(h) No-op

No-op is assigned when Reset, Abort and Start commands are issued.

4.2.4 Data Register

The data register is not a real one but is a general name of the Result, Mod0/1, Exp0/1 and Bas0/1 registers. The read/write operations from/into these registers are performed by accessing the Data register after writing the W/R and Register field of the command register. These operations are only possible when the I/O Ready flag in the Status Register0/1 is "high".

5.  STATUS DESCRIPTION

5.1 Status Transition Table

6. TYPICAL USAGE

This chapter presents the typical usage of NLC0048, from Reset command to reading the result.

6.1 Operation example using Exp0, Mod0, Bas0

-- LSI Reset --

(1) Write Command Register

     Reset field: "high"

     Other fields: "low"

-- Exp0 Writing --

(2) Read Status0 Register, and Check following fields.

     Command Ready: "high"

     Exp0: "high"

          note: Exp0 field is always "high".

     Other fields: "Low"

     If LSI returns other values, it is something invalid.

(3) Write Command Register

     W/R* field: "high" (Write)

     Register field: "3h"(Exp0)

     Other fields: "low"

(4) Read status0, and Check following fields.

     I/O Ready: "high"

     Command Ready: "high"

     Exp0: "high"

          note: Exp0 field is always "high".

     Other fields: "low"

     If LSI returns other values, it is something invalid.

(5) Write Exp0/1 data to Data register by 8 bits from most significant byte.

Note: If Exp0 is already written and held by battery, (2) - (5) steps are not necessary.

-- Mod0 Writing --

(6) Write command Register

     W/R* field: "high" (Write)

     Register field: "5h"(Mod0)

     Other fields: "low"

(7) Read Status0 register repeatedly till fields become following state.

     I/O Ready: "low" --> "high"

     Command Ready: "low" --> "high"

     Exp0: "high"

     Other fields: "low"

(8) Write Mod0 data to Data register by 8 bits from most significant byte.

-- Bas0 Writing --

(9) Write Command Register

     W/R field: "high" (Write)

     Register field: "1h"(Bas0)

     Other fields: "low"

(10) Read Status0 Register repeatedly till fields become following state.

     I/O Ready: "low" --> "high"

     Command Ready: "low" --> "high"

     Exp0: "high"

     Other fields: "low"

(11) Write message data to Data register by 8 bits from most significant byte.

-- Start Command Writing --

(12) Write Command Register

     Start field: "high"

     Other fields: "low"

(13) Read Status0 Register repeatedly till fields become following state.

     Error: "low"

     I/O Ready: "low" --> "high"

     Command Ready: "low" --> "high"

     busy: "high"

     busy0: "high"

     Exp0; "high"

     Mod0: "high"

     Bas0: "high"

-- Abort command writing if necessary --

(14) Write Command Register

     Abort field: "high"

     Other fields: "low"

     Operation can be restarted from (1), (3), (6) or (9).

-- Read command writing --

(15) Write Command Register

     W/R* field: "high" (Write)

     Register field: "7h"(Result)

     Other fields: "low"

(16) Read Status0 Register repeatedly till fields become following state.

     Error: "low"

     I/O Ready: "low" --> "high"

     Command Ready: "low" --> "high"

     busy: "low"

     busy0: "low"

     Exp0; "high"

     Mod0: "high"

     Bas0: "high"

(17) Read resulted data from Data register by 8 bits.

     Operation can be restarted from (1), (3), (6) or (9).

6.2 Operation example using Exp1, Mod1, Bas1

-- LSI Reset --

(1) Write Command Register

     Reset field: "high"

     Other fields: "low"

-- Exp1 Writing --

(2) Read Status1 Register, and Check following fields.

     Command Ready: "high"

     Other fields: "Low"

     If LSI returns other values, it is something invalid.

(3) Write Command Register

     W/R* field: "high" (Write)

     Register field: "4h"(Exp1)

     Other fields: "low"

(4) Read status1, and Check following fields.

     I/O Ready: "high"

     Command Ready: "high"

     Other fields: "low"

     If LSI returns other values, it is something invalid.

(5) Write Exp1 data to Data register by 8 bits from most significant byte.

-- Mod1 Writing --

(6) Write command Register

     W/R* field: "high" (Write)

     Register field: "6h"(Mod1)

     Other fields: "low"

(7) Read Status1 register repeatedly till fields become following state.

     I/O Ready: "low" --> "high"

     Command Ready: "low" --> "high"

     Exp0: "high"

     Other fields: "low"

(8) Write Mod0 data to Data register by 8 bits from most significant byte.

-- Bas1 Writing --

(9) Write Command Register

     W/R field: "high" (Write)

     Register field: "2h"(Bas1)

     Other fields: "low"

(10) Read Status1 Register repeatedly till fields become following state.

     I/O Ready: "low" --> "high"

     Command Ready: "low" --> "high"

     Exp1: "high"

     Mod1: "high"

     Other fields: "low"

(11) Write message data to Data register by 8 bits from most significant byte.

-- Start Command Writing --

(12) Write Command Register

     Start field: "high"

     Other fields: "low"

(13) Read Status1 Register repeatedly till fields become following state.

     Error: "low"

     I/O Ready: "low" --> "high"

     Command Ready: "low" --> "high"

     busy: "high"

     busy1: "high"

     Exp1; "high"

     Mod1: "high"

     Bas1: "high"

-- Abort command writing if necessary --

(14) Write Command Register

     Abort field: "high"

     Other fields: "low"

     Operation can be restarted from (1), (3), (6) or (9).

-- Read command writing --

(15) Write Command Register

     W/R* field: "high" (Write)

     Register field: "7h"(Result)

     Other fields: "low"

(16) Read Status1 Register repeatedly till fields become following state.

     Error: "low"

     I/O Ready: "low" --> "high"

     Command Ready: "low" --> "high"

     busy: "low"

     busy1: "low"

     Exp1; "high"

     Mod1: "high"

     Bas1: "high"

(17) Read resulted data from Data register by 8 bits.

Operation can be restarted from (1), (3), (6) or (9).

7.  ELECTRICAL CHARACTERISTICS

7.1 Maximum Ratings (Ta = 25 degrees C)

7.2 Guaranteed Operating Ranges

7.3 DC Characteristics (Ta = 0~70C V_DD=3.3V+/-5%)

7.4 AC Specifications

                                                                                                          (Unit: nsec)

note-1 Condition: External capacitance is 15pF at output pins.

note-2 The Value in 7 is required to be at least 1 tau [time constant] +5(nsec) for command write.

8.  MECHANICAL DATA

8.1 PIN Assignments

Signal Name

     Vdd: +3.3-volt power supply

     Vss: Ground connections

     NC: No not connect

     #1: Do not connect

     #2: Do pull-up to +3.3-volt

I/O

     I: Input pins.

     O: Output pins.

     B: Bidirectional pins.

8.2 Package Dimensions

[End]

Transcription and HTML by Cryptome.