The following figure illustrates the general architecture of the board.
Now let's step through the subsequent components:
Although this bridge is located along with the critical data path and thus increases latency somewhat it makes a lot of things more easy to realize.
The first thing here is the handling of the Flash EEPROM. The DEC Bridge has an interface to such component where it's possible to integrate a boot ROM with minor additional glue logic. Because there's anyways such ROM needed for FPGA initialization, the boot ROM interface can be used to update the FPGA initialization stream. The lower 256kB of the Flash are intended for boot code while the upper 256kB are needed for FPGA initialization.
Another purpose of the DEC Bridge is simplification of the PCI design.
Because this bridge is a so-called non-transparent PCI-PCI bridge it
is actually not a PCI-PCI bridge following the PCI Specification for
such bridges. Therefore the DEC21554 is visible as a normal PCI device
offering only several address windows. This fact eliminates the need
for implementation of a PCI configuration space inside the PCI FPGA.
The 21554 is also able to make a direct offset translation of primary PCI addresses into secondary PCI addresses. This makes it possible to use hard-coded address decoders inside the PCI FPGA rather than a comparator as it is normally required for PCI.
The PCI FPGA is maybe the most important unit of the whole design because it realizes substantial functions. It is based on an ORCA 3T80 FPGA manufactured by Lucent Technologies. Basic functions of the PCI FPGA are:
Details of the PCI FPGA are quite complicated. There's even a small highly specialized processor integrated to not loose to overview about the design. PCI FPGA internals will be discussed in a separate page later.
The SCI FPGA is based on the same chip as the PCI FPGA (ORCA 3T80).
The functions of the SCI FPGA are concentrated on SCI packet handling.
That is, it is responsible for receiving and sending of SCI
packets from/to the SCI Link Controller. Also, the SCI FPGA is responsible
to detect problems during packet transmission (such as timeouts)
and to take some appropriate actions (such as packet
retransmission) in these cases.
The SCI FPGA is able to support for up to 64 outstanding SCI transactions and up to 63 (maybe also 127) incoming packets.
Below you can see the block diagram of the SCI FPGA. To view the figure at a higher resolution (recommended) please click on it!
The primary function of the Dual Ported Memory (DPM) is storage of SCI packets or rather the data body of SCI packets. Because of the two completely asynchronous and independent ports of this buffer memory it is possible to receive a new SCI packet while data of a formerly received SCI packet is written into PCI memory, for example.
As mentioned previously, actually only the data body of SCI packets have to be stored in the DPM. Other informations (such as address and status) are exchanged between both FPGAs using a different path (see figure). However, because of some constructive reasons whole SCI packets (at least incoming ones) are stored in the DPM for now.
This additional memory contains three large tables:
The basic SRAM size of 1MByte supports 80kEntries for the downstream address
translation table (64bits/entry), 32kEntries for the upstream address translation
table (32bits/entry), and 1kEntries for the VI context memory (256Bytes/entry).
Assuming a page size of 4kBytes for exported and imported memory pages this results in 320MBytes of importable memory and 128MBytes of exportable memory.
The LC-2 made by Dolphin Interconnect Solutions realizes the timing critical functions of the high-speed SCI connections. Actually the LC-2 is able to achive a link bandwidth of 500MByte/s (cumulative bandwidth of 1GByte/s since data is transferred on link-in and link-out in parallel). However, for now we tested it only with a link frequency of 100MHz. That is, the bandwidth of one link is 'only' 400MByte/s.